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Reduction of threshold voltage sensitivity in SOI MOSFET's

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4 Author(s)
M. J. Sherony ; Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA ; L. T. Su ; J. E. Chung ; D. A. Antoniadis

The threshold voltage sensitivity, of fully depleted SOI MOSFET's to variations in SOI silicon film thickness was examined through both simulation and device experiments. The concept of designing the channel V/sub th/ implant to achieve a constant dose within the film, rather than a constant doping concentration, was studied for a given range of film thicknesses. Minimizing the variation in retained dose reduced the threshold voltage sensitivity to film thickness for the range of t/sub si/ examined. One-dimensional process simulations were performed to determine the optimal channel implant condition that would reduce the variation in retained dose using realistic process parameters for both NMOS and PMOS device processes. SOI NMOS transistors were fabricated. The experimental results confirmed the simulation findings and achieved a reduced threshold voltage sensitivity.<>

Published in:

IEEE Electron Device Letters  (Volume:16 ,  Issue: 3 )