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Synthesis of hazard-free asynchronous circuits with bounded wire delays

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3 Author(s)
L. Lavagno ; Dept. of Electr. Eng., Politecnico di Torino, Italy ; K. Keutzer ; A. L. Sangiovanni-Vincentelli

This paper introduces a new synthesis methodology for asynchronous sequential control circuits from a high level specification, the signal transition graph (STG). The methodology is guaranteed to generate hazard-free circuits with the bounded wire-delay model, if the STG is live and has the complete state coding property. The methodology exploits knowledge of the environmental delays, speed-independence with respect to externally visible signals, and logic synthesis techniques. A proof that STG persistency is neither necessary nor sufficient for hazard-free implementation is given

Published in:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  (Volume:14 ,  Issue: 1 )