Scheduled System Maintenance:
Some services will be unavailable Sunday, March 29th through Monday, March 30th. We apologize for the inconvenience.
By Topic

Bisectional fault-tolerant communication architecture for supercomputer systems

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Ghafoor, A. ; Dept. of Electr. & Comput. Eng., Syracuse Univ., NY, USA ; Bashkow, T.R. ; Ghafoor, I.

A highly versatile communication architecture, the bisectional interconnection network, is proposed. These networks possess many attractive features such as small internode distances, ability to do self-routing which is easily extendible to failure conditions, and the capability of maximal fault tolerance. The proposed architecture allows optimal implementation of various logical configurations. Furthermore, the authors propose the use of a combinatorial structure, called the symmetric balanced incomplete block design (SBIBD), to partition these networks. This important property of partitioning allows the system's expansion with fault tolerance and is utilized to describe two semidistributed fault-diagnostic strategies which require remarkably low overhead and at the same time identify a large number of faulty nodes. Furthermore, based on SBIBDs, a unique approach for making the diagnostic scheme itself fault tolerant is proposed

Published in:

Computers, IEEE Transactions on  (Volume:38 ,  Issue: 10 )