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An accurate and efficient delay time modeling for MOS logic circuits using polynomial approximation

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3 Author(s)
Young-Hyun Jun ; Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Seoul, South Korea ; Ki Jun ; Song-Bai Park

A delay model for multiple delay simulation for NMOS and CMOS logic circuits is proposed. For the simple inverter the rise or fall delay time is approximated by a product of polynomials of the input waveform slope, the output loading capacitance, and the device configuration ratio, with the polynomial coefficients determined so as to best fit the SPICE simulation results for a given fabrication process. This approach can easily be extended to the case of multiple-input transitions. The simulation results show that the proposed modes can predict the delay times within 5% error and with a speedup of three orders of magnitude for several circuits tested as compared with the SPICE simulation

Published in:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  (Volume:8 ,  Issue: 9 )