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Developing parallel architectures for range and image sensors

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3 Author(s)
Shaori Guo ; Dept. of Eng. Sci., Oxford Univ., UK ; Luk, W. ; Probert, P.

We describe a cost-effective method for developing parallel architectures which increase the performance of range and image sensors. A parametrised edge detector and its systolic implementation using field-programmable gate arrays (FPGAs) are presented. Experiments and analyses indicate that our circuits can satisfy the performance requirements, and some of the designs out-perform the software equivalent on a 486-based PC by nearly two orders of magnitude

Published in:

Robotics and Automation, 1994. Proceedings., 1994 IEEE International Conference on

Date of Conference:

8-13 May 1994