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Using a resource-limited instruction scheduler to evaluate the iHARP processor

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3 Author(s)
F. L. Steven ; Div. of Comput. Sci., Univ. of Hertfordshire, Hatfield, UK ; G. B. Steven ; L. Wang

RISC processors have approached an execution rate of one instruction per cycle by using pipelining to speed up execution. However, to achieve an execution rate of more than one instruction per cycle, processors must issue multiple instructions in each processor cycle. The paper evaluates the architectural features of iHARP, a VLIW processor with an instruction issue rate of four, which has been developed at the University of Hertfordshire. A distinctive feature of iHARP is the provision of Boolean guards on all instructions. Instructions are then only executed at run time if the attached Boolean guard is true. A second distinctive feature is the use of an ORed indexing addressing mechanism to avoid load delays. The paper evaluates the benefits of both these features and quantifies their performance advantage. Other architectural features evaluated include instruction issue rate, code size, number of data cache ports, number of register file write ports, number of branch units, instruction combining and loop unrolling. The evaluation uses a resource-limited instruction scheduler, specifically developed to re-order code at compile times for parallel execution on iHARP

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IEE Proceedings - Computers and Digital Techniques  (Volume:142 ,  Issue: 1 )