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Automatic verification of asynchronous circuits

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3 Author(s)
Lee, T.W.S. ; British Columbia Univ., Vancouver, BC, Canada ; Greenstreet, M.R. ; Seger, Carl-Johan

Verifying asynchronous designs is difficult, since design errors may manifest themselves only under rare circumstances. This article describes how to model asynchronous designs as programs in synchronized transitions, a general-purpose hardware description language. The authors show how this representation facilitates rigorous, efficient verification

Published in:

Design & Test of Computers, IEEE  (Volume:12 ,  Issue: 1 )