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Designing self-timed devices using the finite automaton model

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3 Author(s)
Varshavsky, V.I. ; Comput. Logic Design Lab., Aizu Univ., Japan ; Marakhovsky, V.B. ; Smolensky, V.

The authors suggest a procedure for designing a self-timed device defined by the finite automaton model. This procedure proves useful when designing these devices using the available synchronous behavior specifications. They illustrate the effectiveness of their procedure by applying it to the design of a stack memory and constant acknowledgement delay counter

Published in:

Design & Test of Computers, IEEE  (Volume:12 ,  Issue: 1 )