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An efficient maximum-redundancy radix-8 SRT division and square-root method

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2 Author(s)
Hobson, R.F. ; Sch. of Comput. Sci., Simon Fraser Univ., Burnaby, BC, Canada ; Fraser, M.W.

A new approach to integrating hardware multiplication, division, and square-root is presented. We use a fully integrated control path which simultaneously reduces part of the redundant partial-remainder and performs a truncated multiplication of the next quotient or square-root digit by the divisor or square-root value. A separate (parallel) full precision iterative multiplier is used for partial remainder production. Strategic details of a radix-8 implementation are discussed. It is shown that a maximally redundant digit set is a viable choice for high performance in this case

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Solid-State Circuits, IEEE Journal of  (Volume:30 ,  Issue: 1 )