By Topic

Electrothermal simulation of electrical overstress in advanced nMOS ESD I/O protection devices

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
C. H. Diaz ; Div. of Integrated Circuits Bus., Hewlett-Packard Co., Palo Alto, CA, USA ; C. Duvvury ; Sung-Mo Kang

For electrical overstress (EOS) and electrostatic discharge (ESD) reliability of submicron ICs, there are currently no available accurate circuit-level simulation tools to analyze and design input/output protection devices. In this paper, we introduce a unique circuit-level electrothermal simulator that can accurately predict the protection device behaviour up to the onset of second breakdown under high-current stress events. The results shown here demonstrate practical application to EOS/ESD robustness in sub-micron technologies.<>

Published in:

Electron Devices Meeting, 1993. IEDM '93. Technical Digest., International

Date of Conference:

5-8 Dec. 1993