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Electrothermal simulation of electrical overstress in advanced nMOS ESD I/O protection devices

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3 Author(s)
Diaz, C.H. ; Div. of Integrated Circuits Bus., Hewlett-Packard Co., Palo Alto, CA, USA ; Duvvury, C. ; Sung-Mo Kang

For electrical overstress (EOS) and electrostatic discharge (ESD) reliability of submicron ICs, there are currently no available accurate circuit-level simulation tools to analyze and design input/output protection devices. In this paper, we introduce a unique circuit-level electrothermal simulator that can accurately predict the protection device behaviour up to the onset of second breakdown under high-current stress events. The results shown here demonstrate practical application to EOS/ESD robustness in sub-micron technologies.<>

Published in:

Electron Devices Meeting, 1993. IEDM '93. Technical Digest., International

Date of Conference:

5-8 Dec. 1993

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