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A parasitic-insensitive area-efficient approach to realizing very large time constants in switched-capacitor circuits

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1 Author(s)
K. Nagaraj ; AT&T Bell Labs., Murray Hill, NJ, USA

A novel switched-capacitor technique for realizing very large time constants is presented. The technique is insensitive to parasitic capacitances and is very area-efficient. It does not require a complicated clocking scheme. The technique yields a complete family of integrators which in turn can be used to realize higher-order filtering functions based on cascaded biquadratic sections or ladder filters. These integrators have been used to implement an experimental 60-Hz notch filter working from a 128-kHz clock

Published in:

IEEE Transactions on Circuits and Systems  (Volume:36 ,  Issue: 9 )