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Performance analysis of the XDAC disk array system

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5 Author(s)
Chiung-San Lee ; Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan ; Tai-Ming Parng ; Jew-Chin Lee ; Cheng-Nan Tsai
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The paper presents an analytical model of a whole disk array architecture, XDAC, which consists of several major subsystems and features: the two-dimensional array structure; IO-bus with split transaction protocol; and cache for processing multiple I/O requests in parallel. Our modelling approach is based on a subsystem access time per request (SATPR) concept, in which we model for each subsystem the mean access time per disk array request. The model is fed with a given set of representative workload parameters and then used to conduct performance analysis for exploring the impact of fork/join synchronization as well as evaluating some architectural design issues of the XDAC system. Moreover, by comparing the SATPRs of subsystems, we can identify the bottleneck for performance improvements

Published in:

Parallel and Distributed Processing, 1994. Proceedings. Sixth IEEE Symposium on

Date of Conference:

26-29 Oct 1994