Referenced Items are not available for this document.
A CAMAC system which provides delays, data compaction and readout of signals from high-rate proportional wire chambers is presented. A delay buffer containing a large, fast shift register constructed from high-speed ECL RAMs (emitter-coupled-logic random-access memories) is described in detail. This provides up to 5 μs of delay with no deadtime for 32 binary data channels at a 20-ns sampling rate. A clock and gate distribution module synchronizes several delay modules for multichamber applications. A microprocessor is used to compact the data, thus reducing the volume before transmission to the main data acquisition system
Published in:
Nuclear Science, IEEE Transactions on
(Volume:36
,
Issue:
1
)
Date of Publication: Feb 1989
- Page(s):
- 826 - 827
- ISSN :
- 0018-9499
- INSPEC Accession Number:
- 3420784
- Digital Object Identifier :
- 10.1109/23.34559
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 06 August 2002
- Issue Date :
- Feb 1989
- Sponsored by :
- IEEE Nuclear and Plasma Sciences Society
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