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A low power low noise amplifier for a 128 channel detector read-out chip

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1 Author(s)
Stanton, J.C. ; Rutherford Appleton Lab., Chilton, Didcot, UK

The design of a low-power, low-noise CMOS (complementary metal oxide semiconductor) amplifier is described. The amplifier was designed using the folded cascode configuration and was implemented on a 3-μm double polysilicon process. The amplifier is part of a 128-channel charge amplifier array chip for use in the readout of radiation detectors with many channels. Aspects of the amplifier design such as bandwidth, pulse response, and noise are discussed, and the effects of individual transistors are shown, thereby relating circuit performance to process parameters. Circuit and radiation test results are included. The results show that a noise level as low as 670 electrons has been achieved with a risetime of 240 ns and a power density of less than 0.45 mW per channel

Published in:

Nuclear Science, IEEE Transactions on  (Volume:36 ,  Issue: 1 )

Date of Publication:

Feb 1989

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