A 125 Mbs CMOS all-digital data transceiver using synchronous uniform sampling

A 125 Mb/s all digital monolithic transceiver circuit using a 0.8 /spl mu/m, double-metal digital CMOS process is intended for the digital transceiver core of a CMOS VLSI FDDI chip. All components used are digital with no biasing or analog control. The circuit recovers any arbitrary binary sequence and is readily implemented in digital CMOS technology.<
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