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Subthreshold MOSFET conduction model and optimal scaling for deep-submicron fully depleted SOI CMOS

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2 Author(s)
Yeh, P.C. ; Dept. of Electr. Eng., Florida Univ., Gainesville, FL, USA ; Fossum, J.G.

In this paper we present results of a comprehensive study of the subthreshold characteristics of deep-submicron fully depleted SOI MOSFETs, and suggest optimal CMOS scaling rules based on PISCES simulations and two-dimensional analytic modeling for circuit simulation. Measurements reveal that the subthreshold swing S, which is nearly ideal at 60 mV for long-channel fully depleted devices, tends to increase drastically as L is scaled to deep-submicron values. Our previous study showed that the front-surface current contributes to the increased S via gate bias-dependent source/drain charge sharing, which reduces the effective threshold voltage. A more recent study shows that current throughout the SOI film body, including the back surface, tends to overwhelm the front-surface current in the subthreshold region, rendering the drain current less dependent on the front-gate bias and hence increasing S even more

Published in:

SOI Conference, 1993. Proceedings., 1993 IEEE International

Date of Conference:

5-7 Oct 1993

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