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Gettering in high resistive float zone silicon wafers for silicon detector applications

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2 Author(s)
Z. Li ; Brookhaven Nat. Lab., Upton, NY, USA ; H. W. Kranar

An intrinsic gettering technique for float-zone highly resistive silicon using TCA+O2 has been described. The capacitance-voltage technique was used to determine the flat-band voltage and stretch-out of MOS (metal oxide semiconductor) structures made on various oxides. It has found that this intrinsic getting process improves minority-carrier-generation lifetime and SiO2/Si interface properties, leading to the reduction of leakage current in the p-i-n detector configuration. Direct comparisons of intrinsic gettering and extrinsic gettering using As ion-implantation have been made. Intrinsic gettering has been found to be the dominant process

Published in:

IEEE Transactions on Nuclear Science  (Volume:36 ,  Issue: 1 )