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Parallel testing of parametric faults in a three-dimensional dynamic random-access memory

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1 Author(s)
Mazumder, P. ; Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA

A testable design of dynamic random-access memory (DRAM) architecture which allows one to access multiple cells in a word line simultaneously is presented. The technique utilizes the two-dimensional (2-D) organization of the DRAM and the resulting speedup of the conventional algorithm is considerable. The failure mechanism in the three-dimensional (3-D) DRAM with trench-type capacitor is specifically investigated. As opposed to the earlier approaches for testing parametric faults that used sliding diagonal-type tests with O(n3/2) complexity, the algorithms discussed here are different and have O(√n/p) complexity, where p is the number of subarrays within the DRAM chip. These algorithms can be applied externally from the chip and also they can be easily generated for built-in self-test applications

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:23 ,  Issue: 4 )