Referenced Items are not available for this document.
This paper presents a scan design for asynchronous sequential logic circuits (ASLCs) using modified SR-latches. With this scan structure, an ASLC is operated in an asynchronous way during the normal operation mode, while it is synchronized with clock signals during the test mode. The modified SR-latch is free of hazards and races for both fault-free and faulty circuits and the scan structure is race-free during normal operation and test modes. The structure achieves full testability of all single stuck-at faults
Published in:
Circuits and Systems, 1993., Proceedings of the 36th Midwest Symposium on
Date of Conference: 16-18 Aug 1993
- Page(s):
- 1300 - 1303 vol.2
- Meeting Date :
- 16 Aug 1993-18 Aug 1993
- Print ISBN:
- 0-7803-1760-2
- INSPEC Accession Number:
- 4852086
- Conference Location :
- Detroit, MI
- Digital Object Identifier :
- 10.1109/MWSCAS.1993.343339
- Product Type:
- Conference Publications
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