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Fault tolerance properties of mesh-connected parallel computers with separable row/column buses

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1 Author(s)
Parhami, B. ; Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA

A two-dimensional processor array with separable row/column buses that are logically divisible into a number of local buses has proven quite effective for a wide class of parallel computations. The author shows how these separable buses, originally proposed for improved performance, can also be used to achieve tolerance to processor and link failures with minimal overhead for certain applications

Published in:

Circuits and Systems, 1993., Proceedings of the 36th Midwest Symposium on

Date of Conference:

16-18 Aug 1993