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A parallel architecture for co-occurrence matrix computation

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3 Author(s)
S. Khalaf ; Dept. of Math., Kuwait Univ., Safat, Kuwait ; M. El-Gabali ; N. Abdelguerfi

Using the odd-even network topology, a parallel hardware architecture for gray level image co-occurrence matrix computation is designed. The architecture consists of simple, regularly structured processing elements (PE's) operating in parallel. As a result, the proposed design is suitable for VLSI implementation. The use of a co-occurrence matrix computational unit of fixed size to handle large images is considered

Published in:

Circuits and Systems, 1993., Proceedings of the 36th Midwest Symposium on

Date of Conference:

16-18 Aug 1993