By Topic

A new algorithm to construct parallel adder for high density codes

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)
Hashemian, Reza ; Dept. of Electr. Eng., Northern Illinois Univ., DeKalb, IL, USA

A new method is presented for high-speed parallel addition. The method is shown to be highly efficient both in terms of silicon area consumption and speed. Here the addition is essentially performed by multiple but simultaneous incrementing procedure, called position-incrementing. The method also utilizes operand partitioning, much similar to the method implemented in carry select addition. The operands, after some initial treatments, are partitioned into small (4-bit) groups, and group additions are then performed independently and concurrently for both cases, one with input carry 1 and the other with 0. Next, the appropriate partial sums are selected based on the actual group carries which are separately processed in a multi-stage multiplexer structure. By implementing a recently developed incrementing circuit, and applying the carry select procedure it is shown that the operational delay is relatively small and it almost increases by O(log 2 n), where n is the word size. The algorithm is implemented for a 64-bit adder. The simulation results show high efficiency both in hardware as well as the speed (gate delays). For the 64-bit adder it is shown that the total hardware used is equivalent to 1186 gates (2 input NAND gates) and the maximum operational delay is about 7.5 unit gate delays

Published in:

Circuits and Systems, 1993., Proceedings of the 36th Midwest Symposium on

Date of Conference:

16-18 Aug 1993