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A single chip high-speed M-to-B arbiter for multiple bus multiprocessor systems

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3 Author(s)
Sheth, D.G. ; Dept. of Electr. & Comput. Eng., Wayne State Univ., Detroit, MI, USA ; Alles, S. ; Mahmud, S.M.

An M-user B-server synchronous arbitration circuit is built on a single chip using NMOS technology. The VLSI layout is modular which consists of 3 basic blocks: Type-1, Type-2, and Type-3. For VLSI layout of each block, one has to perform a few interconnections in order to build M-user B-server arbiter on a single chip. We have justified this statement by building arbiters for 16-user 4-server, 4-user 2-server, and 8-user 2-server. This arbiter design on a single chip can considerably reduce the space for total arbitration circuit in any multiprocessor system. At the same time it is faster and consumes less power

Published in:
Circuits and Systems, 1993., Proceedings of the 36th Midwest Symposium on

Date of Conference: 16-18 Aug 1993

Page(s):
284 - 287 vol.1
Meeting Date :
16 Aug 1993-18 Aug 1993
Print ISBN:
0-7803-1760-2
INSPEC Accession Number:
4839640
Conference Location :
Detroit, MI
Digital Object Identifier :
10.1109/MWSCAS.1993.343074
Product Type:
Conference Publications

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