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A new, precharged, low-power logic family for GaAs circuits

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3 Author(s)
V. Chandramouli ; Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA ; N. Michell ; K. F. Smith

We present a new precharged, low-power logic family in GaAs that operates at speeds comparable to DCFL and consumes about one-fourth the power of DCFL. It uses a 2 V power supply for operation and can be used in conjunction with the widely used DCFL circuits. The logic family allows us to build complex gates in one gate delay, provides better noise margins, and is less susceptible to load capacitances than an unbuffered DCFL gate, thus making it useful for standard-cell based designs. To verify the approach, we have designed and fabricated a fully functional test chip containing a precharged full adder

Published in:

IEEE Journal of Solid-State Circuits  (Volume:30 ,  Issue: 2 )