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A CMOS low-noise and low-power charge sampling integrated circuit for capacitive detector/sensor interfaces

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3 Author(s)
S. Tedja ; Dept. of Electr. Eng., Pennsylvania Univ., Philadelphia, PA, USA ; J. Van der Speigel ; H. H. Williams

This paper describes the design and experimental results of a multichannel calibrationless charge sampling integrated circuit for capacitive detector/sensor interfaces. The integrated circuit incorporates multiple channels of sensitive charge preamplifiers, current/charge-mode amplifiers, pipelined analog storage cells, A/D converters, and static CMOS digital control circuitry. It is implemented in a 1.2 μm single-poly double-metal CMOS p-well technology. The power dissipation is 1 mW/channel. The input-referred equivalent noise charge (ENC) for a detector/sensor source capacitance of 30 pF and an integration time window of 128 ns is 1800 rms electrons. The input-referred channel-to-channel offset variation from chip to chip is only 292 rms electrons while the storage-cell-to-storage-cell offset variation is 142 rms electrons. The channel-to-channel gain variation from chip to chip is 1.6%

Published in:

IEEE Journal of Solid-State Circuits  (Volume:30 ,  Issue: 2 )