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Josephson memory technology

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1 Author(s)
Wada, Yoshifusa ; NEC Corp., Kanagawa, Japan

Memory circuit architecture (decoder, cell, cell array, and sense circuit) is surveyed, with emphasis on implementing a memory with fast access and low power consumption. Recent progress in fabrication and circuit technology has improved memory performance. An AC powering scheme, instead of the earlier DC system, has been developed. The AC powering scheme eliminates complicated timing control, which restricts shortening access time, but introduces large power consumption and in-phase powering problems. A parallel decoding scheme that decreases the number of decoding stages is presented. It will decrease the decoding time and AND scheme decoder. An attractive OR-inverter scheme has been proposed for a decoder suitable for a memory with a large capacity. The chip performance strongly depends not only on whether the read mode is destructive or nondestructive but also on the cell connection method, which determines the line inductance. Because the cell input line inductance depends on layered construction of the lines, a planarizing technology for an Nb Josephson integrated circuit has been developed to reduce line inductance by thinning the insulators. Access time of less than 0.5 ns has been confirmed in 1-kb and 4-kb memories using the proposed memory architecture

Published in:

Proceedings of the IEEE  (Volume:77 ,  Issue: 8 )