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High-density quaternary logic array chip for knowledge information processing systems

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2 Author(s)
Hanyu, T. ; Dept. of Electron Eng., Tohoku Univ., Sendai, Japan ; Higuchi, T.

A high-density NMOS logic array chip based on quaternary logic implemented for high-speed parallel pattern matching in a knowledge information processing system is described. The logic array can be exploited in real-time applications when the rules are fixed. Based on the appropriate quaternary coding for the contents of working memory and production memory, a double-pattern-matching algorithm for achieving a high-density chip is proposed. One of four states for 2-bit information concerning two elements of a rule is stored in a pattern-matching cell by multiple ion implants, so that the pattern-matching cell is implemented using only a single transistor. It is shown that the chip area for pattern matching is reduced by 30% compared with the corresponding binary logic array

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:24 ,  Issue: 4 )

Date of Publication:

Aug 1989

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