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A new CR-delay circuit technology for high-density and high-speed DRAMs

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4 Author(s)
Watanabe, Y. ; Toshiba Corp., Kawasaki, Japan ; Ohsawa, T. ; Sakurai, K. ; Furuyama, T.

The capacitance-resistance (CR) delay circuit technology assures full asynchronicity between memory cell array and peripheral circuits over a wide range of both operating and process conditions and thus realizes a fast access time. A noise compensation scheme is used to generate a constant delay even under the power supply line noise. The circuit was applied to a 4 Mbit dynamic RAM (DRAM) peripheral circuit. As a result, timing loss as well as malfunction could be successfully avoided, and 7 ns faster access time and 39 ns shorter cycle time, compared with a conventional design using normal inverter chains, have been achieved

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:24 ,  Issue: 4 )