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Theoretical study of SEUs in 0.25-/spl mu/m fully-depleted CMOS/SOI technology

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5 Author(s)
Brisset, C. ; Inst. d''Electron. Fondamentale, Univ. de Paris-Sud, Orsay, France ; Dollfus, P. ; Musseau, O. ; Leray, J‐L.
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We present a theoretical study of the behavior of basic CMOS/SOI inverter and static memory cell struck by an energetic ion. This work is based on 3D Monte Carlo device simulation. CMOS cells are made up of ultra-thin SOI film 0.25 /spl mu/m MOSFETs without body ties operating in fully-depleted mode. The ion track is simulated by electron-hole pairs generation with an energy of 1 eV for each carrier. We took a particular care to quantify the radiation effect as a function of linear energy transfer (LET) of the ion. After irradiation of the off-state N-MOS of the inverter, electrons in excess are drained-off by source and drain contacts. Due to the lack of hole contact, excess holes tend to remain accumulated in the channel initiating a parasitic bipolar transistor mechanism. The electron current, flowing from source to drain, discharges the output capacitor, which result in a transient upset. The recovery time is then controlled by recombination of excess holes. For memory cell, even after recombination of excess holes stored in the channel, the return to initial logic state could not be achieved, which constitutes a definitive single event upset (SEU). As this would occur for LET as low as 3 MeV.Cm/sup 2/.Mg/sup -1/, hardening techniques for 0.25 /spl mu/m CMOS/SOI devices are finally discussed.<>

Published in:

Nuclear Science, IEEE Transactions on  (Volume:41 ,  Issue: 6 )

Date of Publication:

Dec. 1994

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