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A 100 MHz A/D interface for PRML magnetic disk read channels

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2 Author(s)
Uehara, G.T. ; Dept. of Electr. Eng., Hawaii Univ., Honolulu, HI, USA ; Gray, P.R.

An analog-to-digital interface IC suitable for PRML read channels with a 100 MHz output rate has been designed and fabricated in a 1.2 μm CMOS technology. The prototype IC contains a low-pass filter, symbol-rate equalizer, analog-to-digital converter, and generates all required clocks from a single external reference clock. The filters are implemented using a switched-capacitor parallel filter architecture used to implement a 3:1 decimation filter and a 3-tap programmable equalizer

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:29 ,  Issue: 12 )

Date of Publication:

Dec 1994

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