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A monolithic 156 Mb/s clock and data recovery PLL circuit using the sample-and-hold technique

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2 Author(s)
N. Ishihara ; NTT LSI Labs., Kanagawa, Japan ; Y. Akazawa

The PLL circuit described here performs the function of data and clock recovery for random data patterns by using a sample-and-hold technique, and four component circuits (a phase comparator, a delay circuit, a voltage-controlled oscillator, and a S/H switch with a low-pass-filter) were specially designed to further stabilize the PLL operation. A test chip fabricated using Si bipolar process technology demonstrated error-free operation with an input of 223-1 PRBS data at 156 Mb/s. The rms data pattern jitter was reduced to only 1.2 degrees with only an external power supply bypass capacitor

Published in:

IEEE Journal of Solid-State Circuits  (Volume:29 ,  Issue: 12 )