Design of a header processor for the PSi implementation of the logical link control protocol in LANs

Fiber optic communications offer a combination of high bandwidth, low error probability, and gigabit transmission capacity. To take advantage of the data transmission rates offered by a fiber optic transmission medium, it is essential to have network processing components that can cope with these rates. One approach to removing the protocol processing bottleneck present in network layers is the PSi architecture. PSi consists of header, connection, and output processors. In this paper, we design a RISC architecture for the PSi header processor. The architecture consists of a two stage pipeline microprogrammed processor with a clock frequency of 50 Megahertz and a throughput of one million packets per second. The specific protocol for which this processor was microprogrammed is the Logical Link Control IEEE 802.2 protocol for LANs.<
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