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Architectural design of a bi-level image high speed codec

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4 Author(s)
Horie, H. ; Tech. Res. & Dev. Lab, Matsushita Graphic Commun. Syst. Inc., Tokyo, Japan ; Ozaki, T. ; Shirai, H. ; Iizuka, Y.

This paper describes a very high speed coding and decoding processor, ImPC (image pipeline codec), which can be applied to an image document retrieval system and a facsimile apparatus because it includes the redundancy reduction coding algorithms: MH (modified Huffman), MR (modified Read), and MMR (modified MR). The ImPC architecture combines pipeline and parallel processing. The ImPC contains a resolution conversion unit, a DMA controller, a 1636×16-bit data RAM, and a microprogram controller with a 3 K×48-bit program ROM, as well as a specific encoder and decoder for MH, MR, and MMR. The ImPC chip is fabricated using 1.2 micron CMOS technology, integrating about 480,000 transistors on a 9.69 mm×10.15 mm die. Experimental results show that the ImPC processes black and white bi-level image data within 2 cycles/pixel. A typical A4 size office document is processed in 0.22 sec including resolution conversion

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Circuits and Systems for Video Technology, IEEE Transactions on  (Volume:4 ,  Issue: 6 )