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Bit-serial multipliers and squarers

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2 Author(s)
Ienne, P. ; Mantra Centre for Neuro-Mimetic Syst., Swiss Federal Inst. of Technol., Lausanne, Switzerland ; Viredaz, M.A.

Traditional bit-serial multipliers present one or more clock cycles of data-latency. In some situations, it is desirable to obtain the output after only a combinational delay, as in serial adders and subtracters. A serial multiplier and a squarer with no latency cycles are presented here. Both accept unsigned or sign-extended two's complement numbers and produce an arbitrarily long output. They are fully modular and thus good candidates for introduction in VLSI libraries

Published in:

Computers, IEEE Transactions on  (Volume:43 ,  Issue: 12 )

Date of Publication:

Dec 1994

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