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A quadruple well, quadruple polysilicon BiCMOS process for fast 16 Mb SRAM's

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16 Author(s)
Hayden, J.D. ; Adv. Products Res. & Dev. Lab., Motorola Inc., Austin, TX, USA ; Taft, R.C. ; Kenkare, P. ; Mazure, C.
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An advanced, high-performance, quadruple well, quadruple polysilicon BiCMOS technology has been developed for fast 16 Mb SRAM's. A split word-line bitcell architecture, using four levels of polysilicon and two self-aligned contacts, achieves a cell area of 8.61 μm2 with conventional I-line lithography and 7.32 μm2 with I-line plus phase-shift or with deep UV lithography. The process features PELOX isolation to provide a 1.0 μm active pitch, MOSFET transistors designed for a 0.80 μm gate poly pitch, a double polysilicon bipolar transistor with aggressively scaled parasitics, and a thin-film polysilicon transistor to enhance bitcell stability. A quadruple-well structure improves soft error rate (SER) and allows simultaneous optimization of MOSFET and bipolar performance

Published in:

Electron Devices, IEEE Transactions on  (Volume:41 ,  Issue: 12 )

Date of Publication:

Dec 1994

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