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A model for a reconfigurable fine-grained optoelectronic processor

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5 Author(s)
Butrym, A.M. ; Dept. of Comput. Sci., Rutgers Univ., New Brunswick, NJ, USA ; Craft, N. ; Guise, D. ; Murdocca, M.
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A model for a dataflow based processor is described in which a program written in a high level language is mapped directly to hardware. The concept is to reconfigure the interconnection network among an array of processing elements (PEs) to match the natural form of a computation, as represented by a dataflow graph. Communication among PEs is handled optically using free-space interconnects. A group of vertical cavity surface emitting lasers (VCSELs) is dedicated to each output port of a PE, which corresponds to an arc in a dataflow graph. Outputs of the VCSELs are imaged through a reconfigurable optical permutation network that redirects beams to their destinations. This combination of optics and electronics may support fine-grained parallelism while balancing time spent in communication with time spent in computation

Published in:

Massively Parallel Processing Using Optical Interconnections, 1994., Proceedings of the First International Workshop on

Date of Conference:

26-27 Apr 1994