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Simultaneous driver and wire sizing for performance and power optimization

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2 Author(s)
Cong, J. ; Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA ; Cheng-Kok Koh

In this paper, we study the simultaneous driver and wire sizing (SDWS) problem under two objective functions: i) delay minimization only, or ii) combined delay and power dissipation minimization. We present general formulations of the SDWS problem under these two objectives based on the distributed Elmore delay model with consideration of both capacitive power dissipation and short-circuit power dissipation. We show several interesting properties of the optimal SDWS solutions under the two objectives, including an important result which reveals the relationship between driver sizing and optimal wire sizing. These results lead to polynomial time algorithms for computing the lower and upper bounds of optimal SDWS solutions under the two objectives, and efficient algorithms for computing optimal SDWS solutions under the two objectives. We have implemented these algorithms and compared them with existing design methods for driver sizing only or independent driver and wire sizing. Accurate SPICE simulation shows that our methods reduce the delay by up to 12%-49% and power dissipation by 26%-63% compared with existing design methods.<>

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Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:2 ,  Issue: 4 )