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Reconciliation of different gate-voltage dependencies of 1/f noise in n-MOS and p-MOS transistors

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3 Author(s)
Scofield, J.H. ; Dept. of Phys., Oberlin Coll., OH, USA ; Borland, Nick ; Fleetwood, D.M.

We have examined the 1/f noise of 3 μm×16 μm, n- and p-MOS transistors as a function of frequency (f), gate-voltage (Vg ) and temperature (T). Measurements were performed for 3 Hz⩽f⩽50 kHz, 100 mV⩽|Vg-Vth|⩽4 V, and 77 K⩽T⩽300 K, where Vth is the threshold voltage. Devices were operated in strong inversion in their linear regimes. At room temperature we find that, for n-MOS transistors, S(Vd)∝Vd2/(Vg-Vth )2, and for p-MOS transistors, we generally find that S(Vd)∝Vd2/(Vg-Vth , consistent with trends reported by others. At lower temperatures, however, the results can be very different. In fact, we find that the temperature dependence of the noise and the gate-voltage dependence of the noise show similar features, consistent with the idea that the noise at a given T and Vg is determined by the trap density, Dt(E), at trap energies E=E(T,Vg). Both the T- and Vg-dependencies of the noise imply that Dt (E) tends to be constant near the silicon conduction band edge, but increases as E approaches the valence band edge. It is evidently these differences in Dt(E) that lead to differences in the gate-voltage dependence of the noise commonly observed at room temperature for n- and p-MOS transistors

Published in:

Electron Devices, IEEE Transactions on  (Volume:41 ,  Issue: 11 )

Date of Publication:

Nov 1994

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