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Tightly-coupled parallel implementations of an avionics algorithm

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2 Author(s)
J. Carter ; Inf. Process. Branch, Wright Res. & Dev. Center, Wright-Patterson AFB, OH, USA ; S. Hary

It has long been recognized that there exists an upper bound on the computing speed attainable with uniprocessor architectures. The state of the industry has been such that the regular performance improvements in silicon technology have kept the need for widespread use of tightly-coupled parallel architectures to a minimum. However, with the increasing computational demands placed upon uniprocessor architectures, the time is rapidly approaching when tightly-coupled parallel architectures will be required. In order to demonstrate the effectiveness of using tightly-coupled parallel architectures for avionics applications, a representative avionics algorithm was parallelized and implemented on three parallel topologies constructed from Texas Instruments' parallel digital signal processor TMS320C40. The algorithm's execution time was measured and estimated on different parallel topologies, including ring, four nearest neighbor mesh, and eight nearest neighbor mesh. It was found that due to the low communication-to-computation ratio of the algorithm, near-linear speedups were obtained for the parallel implementations of the algorithm

Published in:

Aerospace and Electronics Conference, 1994. NAECON 1994., Proceedings of the IEEE 1994 National

Date of Conference:

23-27 May 1994