On a methodology for the design and evaluation of a class of application-oriented parallel computer architectures

A systematic methodology for design and evaluation of a class of application-oriented parallel computer architectures is defined, presented and investigated. The methodology is based on adding quantitative characterizations of communication and computation operators to a model of parallel computation. The general technique (based on an exhaustive enumeration) for implementing the methodology is intractable, and heuristics are defined to implement the methodology in polynomial time. Logical and arithmetic edge characterizations of a graphical representation of the target applications are used to derive guidelines for selective applications of the heuristics. The guidelines may be used to apply a subset of the heuristics when special case redundancies exist, or to apply alternate techniques when some of the heuristics can not be implemented effectively for the target application. A procedure for implementing the guidelines, properties of the heuristics, and related open problems are discussed