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Performance analysis for a cache system with different DRAM designs

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2 Author(s)
Mekhiel, N.N. ; Dept. of Electr. Eng., Ryerson Polytech. Inst., Toronto, Ont., Canada ; McCrackin, D.C.

In this article the ATUM traces are used to study cache system performance with different DRAM designs. The performance of the write back and the write through caches with different cache size and set associativity is discussed. The effect of the DRAM fast page mode and the precharge mode on the overall system performance has been presented. The results show that the cache systems that use DRAM with fast page or precharge design can outperform other systems that use normal DRAM design even with a 2 to 4 times larger cache size. Furthermore, the use of fast page and precharge design helps the fast cache much more than the slow cache

Published in:

Electrical and Computer Engineering, 1993. Canadian Conference on

Date of Conference:

14-17 Sep 1993

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