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Concurrent error detection in high speed carry-free division using alternative input data

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1 Author(s)
Chin-Long Wey ; Dept. of Electr. Eng., Michigan State Univ., East Lansing, MI, USA

Rapid advancements in technology demand innovative computation algorithms and hardware structures to achieve high performance. High speed dividers are commonly designed using SRT division methods. Recently, a high speed carry-free divider design using redundant binary representation has been presented. Based on the carry-free division algorithm and a more general cell fault mode instead of stuck-at fault model, this paper presents a concurrent error detection scheme using alternating input data. The key to the detection of faults is determining that at least one input combination exists for which the error does not result in alternating outputs. Results show that, with a low hardware overhead, the divider circuit is capable of detecting single/multiple transient faults in one cell during the real-time operation and enhancing its reliability significantly

Published in:

Computer Design: VLSI in Computers and Processors, 1994. ICCD '94. Proceedings., IEEE International Conference on

Date of Conference:

10-12 Oct 1994