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Distributed reconfiguration of fault tolerant VLSI multipipeline arrays with constant interstage path lengths

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3 Author(s)
Al-Asaad, H. ; Dept. of Electr. & Comput. Eng., Northeastern Univ., Boston, MA, USA ; Vai, M. ; Feldman, J.

A new fault tolerant multipipeline array architecture and its diagnosis/reconfiguration algorithm is presented. This multipipeline array design methodology is characterized by constant, fault distribution independent interstage path lengths. Other features include a low hardware overhead and a high survival rate when it is compared to existing approaches

Published in:
Computer Design: VLSI in Computers and Processors, 1994. ICCD '94. Proceedings., IEEE International Conference on

Date of Conference: 10-12 Oct 1994

Page(s):
75 - 78
Meeting Date :
10 Oct 1994-12 Oct 1994
Print ISBN:
0-8186-6565-3
INSPEC Accession Number:
4801042
Conference Location :
Cambridge, MA
Digital Object Identifier :
10.1109/ICCD.1994.331858
Product Type:
Conference Publications

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