By Topic

Dynamic probe scheduling optimization for MCM substrate test

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Nan-Chi Chou ; Cadence Design Syst. Inc., San Jose, CA, USA ; Chung-Kuan Cheng ; Russell, T.C.

We propose an improved integrated test generation/optimization algorithm for Multichip Module (MCM) substrate verification using two-probe testers. The goal of this work is to reduce the substrate testing time while providing complete coverage for open, short, and high net resistance faults. We approach this objective via two directions, namely test set size reduction and efficient probe scheduling. The test set size reduction is achieved by eliminating redundant tests associated with conventional approaches. The probe scheduling problem is formulated as a dynamical multi-dimensional Traveling Salesman Problem for probe sequence optimization. A simulated annealing based algorithm is devised to simultaneously take these two factors into consideration during the integrated test generation/optimization process. Since there exist numerous test sets providing complete fault coverage for a given design, our algorithm dynamically selects preferred ones by invoking an efficient validation routine during the test generation/optimization. Experiments conducted on industrial substrates using a two-probe tester showed that the test sets generated by our algorithm are able to reduce the testing time by over 38% compared to those generated by an in-house patented package

Published in:

Components, Packaging, and Manufacturing Technology, Part B: Advanced Packaging, IEEE Transactions on  (Volume:17 ,  Issue: 2 )