By Topic

Parametric yield optimisation of MOS VLSI circuits based on simulated annealing and its parallel implementation

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $31
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Conti, M. ; Dipartimento di Elettronica e Autom., Ancona Univ., Italy ; Orcioni, S. ; Turchetti, C.

As device dimensions continuously scale down in current MOS VLSI technology, statistical tolerances of process parameters become more significant. Thus, for circuit designers, it is essential to estimate the influence of such variations on circuit performances and to optimise the circuit so that the maximum yield is obtained. This paper presents an approach for parametric yield optimisation of MOS VLSI circuits, in which both the simulated annealing and gradient algorithms are combined to improve the computational efficiency. With respect to other methods the proposed approach can be considered more general and robust. In addition, it is able to take deterministic parameters into account and to solve multiobjective problems. To improve the computational efficiency, the method has been implemented in a parallel computing machine based on an array of 16 transputers. Several examples of digital-and analog circuit design optimisation are reported to demonstrate the validity of the approach

Published in:

Circuits, Devices and Systems, IEE Proceedings -  (Volume:141 ,  Issue: 5 )