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A parallel bit-level maximum/minimum selector for digital and video signal processing

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3 Author(s)
Chen-Yi Lee ; Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan ; Shih-Chou Juan ; Wen-Wei Yang

This paper presents a novel circuit for parallel bit-level maximum/minimum selection. The selection is based on a label-updating scheme which sequentially scans a set of data patterns from MSB to LSB and generates corresponding labels. The complete circuit realizing this scheme consists of a set of updating units and a global OR unit, where each updating unit is composed of only a few basic gates. Due to structure modularity, the developed circuit provides a very cost-effective hardware solution for comparing large volumes of data patterns as those required in digital and video signal processing

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IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing  (Volume:41 ,  Issue: 10 )