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Reducing PE/memory traffic in multiprocessors by the difference coding of memory addresses

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1 Author(s)
Koppelman, D.M. ; Dept. of Electr. & Comput. Eng., Louisiana State Univ., Baton Rouge, LA, USA

A method of reducing the volume of data flowing through the network in a shared memory parallel computer (multiprocessor) is described. The reduction is achieved by difference coding the memory addresses in messages sent between processing elements (PE's) and memories. In an implementation, each PE would store the last address sent to each memory, and vice versa. Messages that would normally contain an address instead contain the difference between the address associated with the current and most recent messages. Trace-driven simulation shows that only 70% or less of traffic volume (including data and overhead) is necessary, even in systems using coherent caches. The reduction in traffic could result in a lower cost or lower latency network. The cost of the hardware to achieve this is small, and the delay added is insignificant compared to network latency

Published in:

Parallel and Distributed Systems, IEEE Transactions on  (Volume:5 ,  Issue: 11 )