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Saving power by synthesizing gated clocks for sequential circuits

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3 Author(s)
Benini, L. ; Dept. of Electr. Eng., Stanford Univ., CA, USA ; Siegel, P. ; De Micheli, G.

Portable devices demand low power consumption to prolong battery life. Gating the clock is one strategy for saving power. The authors' technique identifies self-loops in an FSM and uses the function described by the self-loops to gate the clock. Applying these techniques to standard benchmarks achieved an average 25% less power dissipation at a cost of only 5% more area.<>

Published in:

Design & Test of Computers, IEEE  (Volume:11 ,  Issue: 4 )