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A 10-b 125-MHz CMOS digital-to-analog converter (DAC) with threshold-voltage compensated current sources

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2 Author(s)
Chin, S.-Y. ; Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan ; Chung-Yu Wu, Ph.D.

This paper describes a 10-b high-speed COMS DAC fabricated by 0.8-μm double-poly double-metal CMOS technology. In the DAC, a new current source called the threshold-voltage compensated current source is used in the two-stage current array to reduce the linearity error caused by inevitable current variations of the current sources. In the two-stage weighted current array, only 32 master and 32 slave unit current sources are required. Thus silicon area and stray capacitance can be reduced significantly. Experimental results show that a conversion rate of 125 MHz is achievable with differential and integral linearity errors of 0.21 LSB and 0.23 LSB, respectively. The power consumption is 150 mW for a single 5-V power supply. The rise/fall time is 3 ns and the full-scale settling time to ±1/2 LSB is within 8 ns. The chip area is 1.8 mm×1.0 mm

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:29 ,  Issue: 11 )