Referenced Items are not available for this document.
This 512 Kw×8 b×3 way synchronous BiCMOS SRAM uses a 2-stage wave-pipeline scheme, a PLL self-timing generator and a 0.4-μm BiCMOS process to achieve 220 MHz fully-random read/write operations with a GTL I/O interface. Newly developed circuit technologies include: 1) a zig-zag double word-line scheme, 2) a centered bit-line load layout scheme, and 3) a phase-locked-loop (PLL) with a multistage-tapped ring oscillator which generates a clock cycle proportional pulse (CCPP) and a clock edge lookahead pulse (CELP)
Published in:
Solid-State Circuits, IEEE Journal of
(Volume:29
,
Issue:
11
)
Date of Publication: Nov 1994
- Page(s):
- 1317 - 1322
- ISSN :
- 0018-9200
- INSPEC Accession Number:
- 4820611
- Digital Object Identifier :
- 10.1109/4.328630
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 06 August 2002
- Issue Date :
- Nov 1994
- Sponsored by :
- IEEE Solid-State Circuits Society
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